FIG. 1 is a simplified side view of a floating gate FET memory cell 10, and FIG. 2 is a simplified schematic diagram of the floating gate FET memory cell 10 of FIG. 1, in accordance with the prior art. The floating gate FET memory cell 10 includes a source 12, a drain 14, a channel 16 extending from tile source 12 to the drain 14, a floating gate 18 and an externally-accessible control gate 20, all conventionally formed on a semiconductor substrate 22. The floating gate FET memory cell 10 is programmed to store a predetermined amount of charge on the floating gate 18 by application of suitable voltages to the control gate 20, the source 12 and the drain 14.
Application of a positive voltage to the control gate 20 and/or the drain 14 can cause electrons to tunnel through a dielectric layer separating the floating gate 18 from the channel 16. These electrons then charge the floating gate 18, altering a threshold voltage of the floating gate FET memory cell 10. The amount of charge that is stored on the floating gate 18 can later be measured by determining the threshold voltage of the floating gate FET memory cell 10. The more electrons that are stored on the floating gate 18, the more positive the threshold voltage will be.
Application of a suitable voltage to the control gate 20 can cause electrons stored on the floating gate 18 to tunnel out from the floating gate 18, thus erasing the data that were stored in the floating gate FET memory cell 10. Typically, a verify operation is employed at the beginning and the end of each programming operation to determine the status of the floating gate FET memory cell 10.
When the verify operation determines that the status of the floating gate FET memory cell 10 is not what it should be, the programming or erasing operations and the verify operation may be repeated until the verify operation verifies that the floating gate FET memory cell 10 has reached the desired status. When a predetermined number of these operations fail to provide the desired status, the floating gate FET memory cell 10 is deemed defective and is not used again.
Floating gate FET memory cells 10 can be programmed in several different ways. In a first mode of operation, digital data, i.e., logic "0" or logic "1", are stored in each of the floating gate FET memory cells 10. Because the exact value of the threshold voltage shift is not of great concern, digital values can be rapidly programmed by application of a relatively large voltage pulse to the floating gate FET memory cell 10 to ensure at least a certain minimum threshold voltage.
In a second mode of operation, analog data are stored in each of the floating gate FET memory cells 10. In this mode, the amount of threshold voltage shift is of great concern, because this amount is what represents the stored data. Additionally, the tunneling process tends to be somewhat stochastic, because tunneling is a random process, manufacturing variations are random and because the programming behavior of any one floating gate FET memory cell 10 is, to some extent, a function of the prior history of that floating gate FET memory cell 10. As a result, analog data storage is carried out by application of one or more programming pulses to the floating gate FET memory cell 10, followed by reading the threshold voltage of the floating gate FET memory cell 10, comparison of the read value to the desired value and application of further programming pulses as needed.
The programming pulses used in analog programming of floating gate FET memory cells 10 may be longer than those used for digital programming and may have different amplitudes. Because programming each analog value requires both applying multiple pulses and conducting multiple readings of the value stored in the floating gate FET memory cell 10 that is being programmed, programming of analog values takes much longer than programming of digital values. Pulses after the first or subsequent verify read operation during an analog programming sequence may be advantageously modified using results read after the preceding programming pulse or pulses to determine subsequent pulse parameters.
FIG. 3 is a graph simulating stored multi-level analog value variations in a population of the floating gate FET memory cells 10 of FIGS. 1 and 2, in accordance with the prior alt. In FIG. 3, distributions of threshold voltages 30, 32, 34, 36 correspond to specific individual analog values each stored in an individual floating gate FET memory cell 10. Hatched regions separating the voltage ranges 30, 32, 34, 36 correspond to forbidden voltage ranges 38. The forbidden voltage ranges 38 are threshold voltage values that are not programmed into the floating gate FET memory cells 10. These ranges 38 facilitate determination of the analog value represented by a threshold voltage measured during a read operation on a given floating gate FET memory cell 10.
Storage of analog or digital data using floating gate FET memory cells 10 allows a memory device to be programmed with new data. Analog data storage provides data density advantages relative to digital data storage, because storage of discrete levels of charge on a floating gate FET memory cell 10 allows information content equivalent to a number of bits to be stored in the same physical area that a single digital bit can be stored in.
However, the density advantages provided by storage of analog data are offset by several other considerations. More programming time is required to store analog data, because multiple programming pulses are required, the programming pulses may be longer and because the read and verification operations are also longer. Conventional incremental-step pulse programming, while providing greater control over the amount of charge stored on the floating gate 18 and thus providing tighter control over programmed threshold voltage shifts, also may require more time in order to verify the programmed threshold voltage shift. Additionally, longer read times are typically required, because the settling times involved in reading analog values are longer than those for digital values.
A further consideration is that the time required for a given amount of charge to leak into or out of the floating gate 18 is the same for both types of memories, but the degree to which stored data are corrupted by a given amount of charge leakage is markedly greater for analog data than for digital data. As a result, the period for which stored data can be expected to be valid is substantially greater for digital data stored in floating gate FET memory cells 10 than for analog data stored in floating gate FET memory cells 10 having comparable dimensions and other characteristics.